The designers of chips connect cores, which comprise logic cells. Certain software, for chip design, displays chip floorplans. Floorplans define various physical regions, in which the logic cells of certain cores can be placed and blockages where no logic cells can be placed.
Cores have standard interfaces. A network-on-chip (NoC) is an efficient and widely used mechanism for connecting cores. A NoC connects cores through their interfaces, and allows the cores to communicate with each other. A NoC includes logic cells, which are placed throughout the floorplan, and wires, which are routed throughout the floorplan.
A NoC is a network, including connected elements. Some such elements are network interface units, switches, pipeline stages, data width converters, clock domain adapters, power domain adapters, firewalls, and probes. Each element has an approximate physical location within the floorplan.
A NoC connects elements to one another in a network. The organization of connections between elements is the NoC topology.
It is difficult to determine the best NoC topology without a view of the floorplan and how the NoC fits into the floorplan. One conventional approach is to organize the NoC topology based on quality-of-service requirements of cores. For example, one might connect low memory latency cores closest to a memory interface core. Another conventional approach is to group cores based on function. For example, one might group video encoding and decoding cores within the NoC topology. Another conventional approach is to minimize the importance of the spatial distribution of the elements of the NoC within the floorplan by placing the NoC entirely within a central portion of the chip.
Conventional approaches suffice for chips with small numbers of core and simple floorplans. However, chips include increasingly many cores and have correspondingly complex floorplans. What is needed is a method and system to design a NoC topology within the physical constraints of a floorplan.